Hamburg / June 10, 2025 - June 13, 2025
ISC High Performance 2025
Fair for High-Performance Computing, Machine Learning (ML), Data Analysis and Quantum Computing
Website ISC High Performance 2025
Booth L40
Fair for High-Performance Computing, Machine Learning (ML), Data Analysis and Quantum Computing
Website ISC High Performance 2025
Booth L40
The ISC High Performance Conference and Exhibition 2025 is an international forum that brings together experts from research, business and industry to discuss high-performance computing (HPC), artificial intelligence (AI), data analytics and quantum computing. The aim of the event is the global exchange of knowledge, innovation and collaboration in these sectors.
Our experts Dr. Jens Krüger, Dr. Franz-Josef Pfreund, Dr. Mirko Rahn, Dr. Arcesio Castaneda Medina, Dr. Daniel Grünwald and Dr. Pascal Halffmann present their innovations in the research fields of artificial intelligence, quantum computing, scalable computing and next-generation storage systems. The latest developments in the field of parallel high-performance file systems will be presented by our researchers together with colleagues from the Fraunhofer spin-off ThinkParQ.
This year new at ISC High Peformance: Our researchers present MCSS, a flexible, multi-tiered storage architecture designed for ultra-low-latency access in data-intensive workloads. MCSS bridges the performance gap between DRAM and traditional storage, making it ideal for AI inference, real-time analytics, and large-scale simulations.
They also highlight this year GPI-2, their low-overhead, partitioned global address space (PGAS) communication library designed for scalable, latency-sensitive HPC applications. GPI-2 now supports libfabric, expanding compatibility with modern high-performance interconnects and enhancing portability across diverse HPC platforms.
GaspiLS is our scalable iterative solver library, which has already proven itself in industrial companies in times of exascale computing. Many simulations in engineering are based on computational fluid dynamics and finite element methods (CFD and FEM methods), for example the determination of aerodynamic properties of aircraft or the analysis of building statics. To gain faster insights from these simulations, we have developed the linear iterative solver library GaspiLS.
More information about GaspiLS can be found here.
The Global Address Space Programming Interface (GPI) is an asynchronous communication model. Each processor can access all data directly at will – regardless of which memory it is stored in and without affecting other processes running in parallel. It therefore provides a crucial building block for realizing the next supercomputers. The Global Address Space Programming Interface is not developed as a parallel programming language, but as a parallel programming interface that is used universally.
You can find more information about GPI here.
The NASE (Neural Architecture Search Engine) at FraunhoferITWM is a powerful AI tool designed to optimize NeuralNetwork models towards the underlying hardware – e.g. AIaccelerators, customs AISCs and FPGAs. This serviceautomates the process of finding efficient AI models tailoredto specific performance needs such as speed, latency andpower consumption. By incorporating unique hardwarecharacteristics into model design, NASE ensures that eachneural architecture is both optimal and custom-fitted to theuser's requirements. This solution leverages advancedalgorithms and extensive computing resources to deliverready-to-use, efficient neural networks for real-worldapplications.
More information about NASE can be found here.
With the open source multi-user software stack CARME, several users can manage the available resources of a computing cluster. Our software combines machine learning with high-performance (HPC) clusters: the integration of interactive cluster usage gives users the opportunity to use familiar data analysis tools on a complex HPC cluster.
More information about CARME can be found here.
This year, the Fraunhofer ITWM booth will feature the STXProcessor card, showcasing the PCIe 5 Board equipped withfour STX chiplets. These chiplets excel in bandwidth-limitedapplications, particularly with stencil algorithms.
The system offers developers a user-friendly programminginterface through a C++ and OpenMP layer, efficientlymasking the underlying complexity. Our compiler team hassuccessfully optimized this setup to deliver peak performanceacross various simulation kernels, streamlining developmentand enhancing computational efficiency.
More information about STX-Processors can be found here.